1. Field of the Invention
The present invention generally relates to device modeling and to an improved model that simulates proximity effects from adjacent structures.
2. Description of the Related Art
Today's fast-paced product development cycles necessitate that design tools such as device models that simulate the performance of integrated circuit structures be as accurate as possible. Simulator tools have been created that determine the device parametrics of a given integrated circuit structure as a function of the process utilized to form it. See for example U.S. Pat. No. 5,761,481, “Semiconductor Simulator Tool for Experimental N-Channel Transistor Modeling” and “Influence of High Substrate Doping Levels on the Threshold Voltage and the Mobility of Deep-Submicrometer MOSFET's,” 1992 IEEE Transactions on Electron Devices, Vol. 39, No. 4, pp. 932-938. This is particularly true for compact models (e.g., the physics-based subroutines used in numerical simulation codes for larger entities such as circuits, mechanical systems, etc.). To create accurate compact models, measured data are needed from hardware to calibrate the model. Compact models are further discussed and described in patent application Ser. No. 10/023,235, “System and Method For Target-Based Compact Modeling” filed Jan. 7, 2002 and assigned to the assignee of the present invention.
In the art, it is known that “proximity effects” can alter one or more parameters of integrated circuit structures that are adjacent (in “proximity”) to one another. Examples of three different types of proximity effects are described below.
A first proximity effect is the lateral scattering of implanted dopants from a masking image placed nearby the feature of interest. A specific example is the formation of the implanted well regions for CMOS devices. When a well is implanted during manufacturing, implanted ions are scattered laterally across the wafer surface. This unwanted doping can be detected as far from the mask edge as two microns. Design rules allow for FETs to be placed well within this affected area and the result is a FET with a substantially altered threshold of voltage (Vt). Depending on the proximity, the Vt can be altered by as much as 100 mV. This effect can cause performance problems and in worst case scenarios, circuit failure. See e.g. U.S. patent application Ser. No. 10/063,406, entitled “Method of Forming Retrograde N-Well and P-Well”, filed Apr. 19, 2002 and assigned to the assignee of the present invention, for a further discussion of this problem.
A second proximity effect is the proximity of an FET to an isolation edge (such as an edge of a shallow trench isolation, or STI), which can modify the strain (and hence mobility of carriers) in the portion of substrate that provides the channel of the FET. See for example Frim et al, “Strained Si NMOSFETs for High Performance CMOS Technology,” 2001 Symposium on VLSI Technology Digest of Technical Papers, 5B-4, page 59.
A third proximity effect is the differential in integrity of the depth of focus (DOF) of an image printed by a photoexposure tool between a pattern of structures that are wider apart and a pattern of structures that are closer together. Typically this problem is corrected by adding serifs or other sub-resolution “dummy” structures to the photomask. See for example U.S. Pat. No. 5,447,810, “Masks for Improved Lithographic Patterning for Off-Axis Illumination Lithography,” and U.S. Pat. No. 5,821,014, “Optical Proximity Correction Method For Intermediate-Pitch Features Using Sub-Resolution Scattering Bars on a Mask.”
The foregoing and other proximity effects will only become more pervasive as circuit groundrules continue to shrink. A need exists in the art to develop a device modeling and simulation methodology that takes these and other proximity effects into account.